View ISPGAL22V10C-7LK_1750367.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ispgal?22v10 device datasheet june 2010 all devices discontinued! product change notifications (pcns) have been issued to discontinue all devices in this data sheet. the original datasheet pages have not been modi fied and do not reflect those changes. please refer to the table below for refe rence pcn and current product status. product line ordering part number product status reference pcn ispgal22v10c-7lj ispgal22v10c-7ljn pcn#06-07 ispgal22v10c-10lj ispgal22v10c-10ljn ispgal22v10c-15lj ispgal22v10c-15ljn ispgal22v10c-15lji ISPGAL22V10C-7LK ispgal22v10c-10lk ispgal22v10c-15lk ispgal22v10c ispgal22v10c-15lki discontinued pcn#09-10 5555 n.e. moore ct. z hillsboro, oregon 97124-6421 z phone (503) 268-8000 z fax (503) 268-8347 internet: http://www.latticesemi.com
ispgal22v10 in-system programmable e 2 cmos pld generic array logic? 1 description the ispgal22v10, at 7.5ns maximum propagation delay time, combines a high performance cmos process with electrically eras- able (e 2 ) floating gate technology to provide the industry's first in- system programmable 22v10 device. e 2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. the generic architecture provides maximum design flexibility by al- lowing the output logic macrocell (olmc) to be configured by the user. the ispgal22v10 is fully function/fuse map/parametric com- patible with standard bipolar and cmos 22v10 devices. the stan- dard plcc package provides the same functional pinout as the standard 22v10 plcc package with no-connect pins being used for the isp interface signals. unique test circuitry and reprogrammable cells allow complete ac, dc, and functional testing during manufacture. as a result, lat- tice semiconductor delivers 100% field programmability and func- tionality of all gal products. in addition, 10,000 erase/write cycles and data retention in excess of 20 years are specified. features ? in-system programmable? (5-v only) ? 4-wire serial programming interface ? minimum 10,000 program/erase cycles ? built-in pull-down on sdi pin eliminates discrete resistor on board (ispgal22v10c only) ? high performance e 2 cmos ? technology ? 7.5 ns maximum propagation delay ? fmax = 111 mhz ? 5 ns maximum from clock input to data output ? ultramos ? advanced cmos technology ? active pull-ups on all logic input and i/o pins ? compatible with standard 22v10 devices ? fully function/fuse-map/parametric compatible with bipolar and cmos 22v10 devices ?e 2 cell technology ? in-system programmable logic ? 100% tested/100% yields ? high speed electrical erasure (<100ms) ? 20 year data retention ? ten output logic macrocells ? maximum flexibility for complex logic designs ? applications include: ? dma control ? state machine control ? high speed graphics processing ? software-driven hardware configuration ? electronic signature for identification ? lead-free package options copyright ? 2004 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. august 2004 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com plcc sdo i/o/q i/o/q i/o/q 228 i i mode i i i 5 11 14 16 19 25 4 7 9 12 18 21 23 26 i i/o/q i/o/q i/o/q i i i/o/q i/clk i/o/q vcc sclk i/o/q i/o/q i sdi gnd i i vcc i/o/q i/o/q i/o/q i/o/q i/o/q sdo i/o/q i/o/q i/o/q i/o/q i/o/q i sdi sclk i/clk i i i i i mode i i i i i gnd 1 7 14 28 22 15 ispgal 22v10 top view ssop ispgal22v10 top view isp22v10_04 functional block diagram pin configuration lead-free package options available! programmable and-array (132x44) i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q sdo sdi mode sclk i/clk i i i i i i i i i i reset preset 8 10 12 14 16 16 14 12 10 8 olmc olmc olmc olmc olmc olmc olmc olmc olmc olmc programming logic i all devices discontinued
specifications ispgal22v10 2 ordering information conventional packaging commercial grade specifications industrial grade specifications )sn(dp t) sn(us t) sn(oc t) am(cc i# gniredr oe gakcap 5 10 18 5 6 1i jl51-c01v22lagps ic clpdael-82 01v22lagps ic - 5 1l i kd ael-8 2p oss part number description blank = commercial i = industrial grade package power l = low power speed (ns) xxxxxxxx xx x xx x device name _ j = plcc jn = lead-free plcc k = ssop ispgal22v10c lead-free packaging commercial grade specifications 1. discontinued per pcn #06-07. contact rochester electronics for available inventory. )sn(dp t) sn(us t) sn(oc t) am(cc i# gniredr oe gakcap 5. 75 . 65 0 4 1j l7-c01v22lagpsi 1 cclpdael-82 01v22lagps ic l 7 -k d ael-8 2p oss 0 177 0 4 1j l01-c01v22lagps ic clpdael-82 01v22lagps ic - 0 1lk d ael-8 2p oss 5 10 18 0 4 1j l51-c01v22lagps ic clpdael-82 01v22lagps ic - 5 1lk d ae l-8 2p oss )sn(dp t) sn(us t) sn(oc t) am(cc i# gniredr oe gakcap 5. 75 . 65 0 4 1n jl7-c01v22lagpsi 1 cclpdael-82eerf-dael 0 177 0 4 1n jl01-c01v22lagps ic clpdael-82eerf-dael 5 10 18 0 4 1n jl51-c01v22lagps ic clpdael-82eerf-dael all devices discontinued
specifications ispgal22v10 3 ispgal22v10 output logic macrocell (olmc) each of the macrocells of the ispgal22v10 has two primary func- tional modes: registered, and combinatorial i/o. the modes and the output polarity are set by two bits (so and s1), which are nor- mally controlled by the logic compiler. each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. registered in registered mode the output pin associated with an individual olmc is driven by the q output of that olmc?s d-type flip-flop. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). output tri-state control is available as an in- dividual product-term for each olmc, and can therefore be defined by a logic equation. the d flip-flop?s /q output is fed back into the and array, with both the true and complement of the feedback available as inputs to the and array. note: in registered mode, the feedback is from the /q output of the register, and not from the pin; therefore, a pin defined as reg- istered is an output only, and cannot be used for dynamic i/o, as can the combinatorial pins. combinatorial i/o in combinatorial mode the pin associated with an individual olmc is driven by the output of the sum term gate. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). out- put tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either ?on? (dedicated output), ?off? (dedicated input), or ?product-term driven? (dynamic i/o). feedback into the and array is from the pin side of the output enable buffer. both polarities (true and inverted) of the pin are fed back into the and array. the ispgal22v10 has a variable number of product terms per olmc. of the ten available olmcs, two olmcs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two olmcs have sixteen product terms (pins 21 and 23). in addition to the product terms available for logic, each olmc has an additional product-term dedicated to output enable control. the output polarity of each olmc can be individually programmed to be true or inverting, in either combinatorial or registered mode. this allows each output to be individually configured as either active high or active low. the ispgal22v10 has a product term for asynchronous reset (ar) and a product term for synchronous preset (sp). these two prod- uct terms are common to all registered olmcs. the asynchronous reset sets all registers to zero any time this dedicated product term is asserted. the synchronous preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. note: the ar and sp product terms will force the q output of the flip-flop into the same state regardless of the polarity of the output. therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. ar sp d q q clk 4 to 1 mux 2 to 1 mux output logic macrocell (olmc) output logic macrocell configurations all devices discontinued
specifications ispgal22v10 4 active high active low active high active low s 0 = 1 s 1 = 1 s 0 = 0 s 1 = 1 s 0 = 0 s 1 = 0 s 0 = 1 s 1 = 0 ar sp d q q clk ar sp d q q clk registered mode combinatorial mode all devices discontinued
specifications ispgal22v10 5 2 26 olmc s0 5810 s1 5811 0440 . . . . 0880 3 asynchronous reset (to all registers) 0 4 8 1216202428323640 synchronous preset (to all registers) 12 0000 5764 0044 . . . 0396 27 s0 5808 s1 5809 25 olmc s0 5812 s1 5813 0924 . . . . . 1452 4 5 6 24 olmc s0 5814 s1 5815 1496 . . . . . . 2112 23 olmc s0 5816 s1 5817 2156 . . . . . . . 2860 21 olmc s0 5818 s1 5819 2904 . . . . . . . 3608 20 olmc s0 5820 s1 5821 3652 . . . . . . 4268 olmc s0 5822 s1 5823 4312 . . . . . 4840 10 19 18 olmc s0 5824 s1 5825 4884 . . . . 5324 11 5368 . . . 5720 17 olmc s0 5826 s1 5827 9 7 13 16 8 10 14 16 12 12 16 14 10 8 olmc electronic signature 5828, 5829 ... ... 5890, 5891 l s b m s b byte 7 byte 6 byte 5 byte 4 byte 2 byte 1 byte 0 byte 3 ispgal22v10 logic diagram/jedec fuse map plcc & ssop package pinout all devices discontinued
specifications ispgal22v10 6 v il input low voltage vss ? 0.5 ? 0.8 v v ih input high voltage 2.0 ? vcc+1 v i il input or i/o low leakage current 1 0v v in v il (max.) ? ? ?100 a sdi low leakage current 2 0v v in v il (max.) ? ? 250 a i ih input or i/o high leakage current 3.5v v in v cc ??10 a sdi high leakage current 2 v in = v oh (min.) ? ? 1 ma v ol output low voltage i ol = max. vin = v il or v ih ? ? 0.5 v v oh output high voltage i oh = max. v in = v il or v ih 2.4 ? ? v i ol low level output current ? ? 16 ma i oh high level output current ? ? ?3.2 ma i os 3 output short circuit current v cc = 5v v out = 0.5v t a = 25 c ?30 ? ?130 ma recommended operating conditions commercial devices: ambient temperature (t a ) ............................. 0 to +75 c supply voltage (v cc ) with respect to ground ..................... +4.75 to +5.25v industrial devices: ambient temperature (t a ) ............................ -40 to 85 c supply voltage (v cc ) with respect to ground ..................... +4.50 to +5.50v symbol parameter condition min. typ. 4 max. units commercial i cc operating power v il = 0.5v v ih = 3.0v l -7/-10/-15 ? 90 140 ma supply current f toggle = 15mhz outputs open absolute maximum ratings (1) supply voltage v cc ....................................... - 0.5 to +7v input voltage applied ........................... -2.5 to v cc +1.0v off-state output voltage applied .......... -2.5 to v cc +1.0v storage temperature ................................. -65 to 150 c ambient temperature with power applied ......................................... -55 to 125 c 1. stresses above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. these are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). specifications ispgal22v10c 1) the leakage current is due to the internal pull-up on all pins (except sdi on ispgal22v10c). see input buffer section for more information. 2) the leakage current is due to the internal pull-down on the sdi pin (ispgal22v10c only). see input buffer section for more information. 3) one output at a time for a maximum duration of one second. vout = 0.5v was selected to avoid test problems caused by teste r ground degradation. characterized but not 100% tested. 4) typical values are at vcc = 5v and t a = 25 c industrial i cc operating power v il = 0.5v v ih = 3.0v l -15 ? 90 165 ma supply current f toggle = 15mhz outputs open dc electrical characteristics over recommended operating conditions (unless otherwise specified) all devices discontinued
specifications ispgal22v10 7 -15 min. max. -10 min. max. -7 min. max. t pd a input or i/o to combinatorial output ? 7.5 ? 10 ? 15 ns t co a clock to output delay ? 5 ? 7 ? 8 ns t cf 2 ? clock to feedback delay ? 2.5 ? 2.5 ? 2.5 ns t su 1 ? setup time, input or feedback before clock 6.5 ? 7 10 ? ns t su 2 ? setup time, sp before clock 10 ? 10 ? 10 ? ns t h ? hold time, input or feedback after clock 0?0? 0 ? ns a maximum clock frequency with 87 ? 71.4 ? 55.5 ? mhz external feedback, 1/(tsu + tco) f max 3 a maximum clock frequency with 111 ? 105 ? 80 ? mhz internal feedback, 1/(tsu + tcf) a maximum clock frequency with 111 ? 105 ? 83.3 ? mhz no feedback t wh ? clock pulse duration, high 4 ? 4 ? 6 ? ns t wl ? clock pulse duration, low 4 ? 4 ? 6 ? ns t en b input or i/o to output enabled ? 8 ? 10 ? 15 ns t dis c input or i/o to output disabled ? 8 ? 10 ? 15 ns t ar a input or i/o to asynchronous reset of register ? 13 ? 13 ? 20 ns t arw ? asynchronous reset pulse duration 8 ? 8 ? 15 ? ns t arr ? asynchronous reset to clock recovery time 8 ? 8 ? 10 ? ns t spr ? synchronous preset to clock recovery time 10 ? 10 ? 10 ? ns parameter units test cond. 1 description com com/ind com 1) refer to switching test conditions section. 2) calculated from fmax with internal feedback. refer to fmax description section. 3) refer to fmax description section. symbol parameter maximum* units test conditions c i input capacitance 8 pf v cc = 5.0v, v i = 2.0v c i/o i/o capacitance 8 pf v cc = 5.0v, v i/o = 2.0v *characterized but not 100% tested. specifications ispgal22v10c ac switching characteristics over recommended operating conditions capacitance (t a = 25 c, f = 1.0mhz) all devices discontinued
specifications ispgal22v10 8 input or i/o to output enable/disable registered output combinatorial output f max with feedback clock width t en t dis input or i/o feedback output clk (w/o fdbk) t wh t wl 1/ f max input or i/o feedback registered output clk valid input t su t co t h (external fdbk) 1/ f max clk registered feedback t cf t su 1/ f max (internal fdbk) registered output clk t arw t arr input or i/o feedback driving ar t ar asynchronous reset registered output clk input or i/o feedback driving sp t su t h t co t spr synchronous preset valid input input or i/o feedback t pd combinatorial output switching waveforms all devices discontinued
specifications ispgal22v10 9 input pulse levels gnd to 3.0v input rise and fall times 3ns 10% ? 90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure 3-state levels are measured 0.5v from steady-state active level. output load conditions (see figure) test condition r 1 r 2 c l a 300 390 50pf b active high 390 50pf active low 300 390 50pf c active high 390 5pf active low 300 390 5pf f max with internal feedback 1/( t su+ t cf) note: tcf is a calculated value, derived by sub- tracting tsu from the period of fmax w/internal feedback ( t cf = 1/ f max - t su). the value of t cf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. for example, the timing from clock to a combi- natorial output is equal to tcf + tpd. f max with no feedback note: f max with no feedback may be less than 1/ t wh + t wl. this is to allow for a clock duty cycle of other than 50%. register logic array t co t su clk note: f max with external feedback is cal- culated from measured tsu and tco. f max with external feedback 1/( t su+ t co) test point c * l from output (o/q) under test +5v *c l includes test fixture and probe capacitance r 2 r 1 clk register logic array t cf t pd register logic array clk t su + t h f max descriptions switching test conditions all devices discontinued
specifications ispgal22v10 10 electronic signature an electronic signature (es) is provided in every ispgal22v10 device. it contains 64 bits of reprogrammable memory that can contain user-defined data. some uses include user id codes, revision numbers, or inventory control. the signature data is always available to the user independent of the state of the security cell. the electronic signature is an additional feature not present in other manufacturers' 22v10 devices. to use the extra feature of the user-programmable electronic signature it is necessary to choose a lattice semiconductor 22v10 device type when compil- ing a set of logic equations. in addition, many device program- mers have two separate selections for the device, typically an ispgal22v10 and a ispgal22v10-ues (ues = user electronic signature) or ispgal22v10-es. this allows users to maintain compatibility with existing 22v10 designs, while still having the option to use the gal device's extra feature. the jedec map for the ispgal22v10 contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. however, the ispgal22v10 device can still be programmed with a standard 22v10 jedec map (5828 fuses) with any qualified device pro- grammer. security cell a security cell is provided in every ispgal22v10 device to prevent unauthorized copying of the array patterns. once pro- grammed, this cell prevents further read access to the functional bits in the device. this cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. the electronic signature is always available to the user, regardless of the state of this control cell. latch-up protection ispgal22v10 devices are designed with an on-board charge pump to negatively bias the substrate. the negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. additionally, outputs are designed with n- channel pullups instead of the traditional p-channel pullups to eliminate any possibility of scr induced latching. device programming the ispgal22v10 device uses a standard 22v10 jedec fusemap file to describe the device programming information. any third party logic compiler can produce the jedec file for this device. in-system programmability the ispgal22v10 device features in-system programmable technology. by integrating all the high voltage programming circuitry on-chip, programming can be accomplished by simply shifting data into the device. once the function is programmed, the non-volatile e 2 cmos cells will not lose the pattern even when the power is turned off. all necessary programming is done via four ttl level logic interface signals. these four signals are fed into the on-chip programming circuitry where a state machine controls the pro- gramming. the interface signals are serial data in (sdi), serial data out (sdo), serial clock (sclk) and mode (mode) control. for details on the operation of the internal state machine and programming of ispgal22v10 devices please refer to the isp architecture and programming section in this data book. output register preload when testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. this is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). to test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. then the machine can be sequenced and the outputs tested for correct next state condi- tions. the ispgal22v10 device includes circuitry that allows each registered output to be synchronously set either high or low. thus, any present state condition can be forced for test sequencing. if necessary, approved gal programmers capable of executing test vectors perform output register preload automatically. input buffers ispgal22v10 devices are designed with ttl level compatible input buffers. these buffers have a characteristically high imped- ance, and present a much lighter load to the driving logic than bipolar ttl devices. all input and i/o pins (except sdi on the ispgal22v10c) also have built-in active pull-ups. as a result, floating inputs will float to a ttl high (logic 1). the sdi pin on the ispgal22v10c has a built-in pull-down to keep the device out of the programming state if the pin is not actively driven. however, lattice semiconductor recommends that all unused inputs and tri-stated i/o pins be connected to an adjacent active input, vcc, or ground. doing so will tend to improve noise immunity and reduce icc for the device. (see equivalent input and i/o schematics on the following page.) typical input current 1.0 2.0 3.0 4.0 5.0 -60 0 -20 -40 0 input voltage (volts) input current ( a) all devices discontinued
specifications ispgal22v10 11 power-up reset vcc (min.) t pr internal register reset to logic "0" device pin reset to logic "1" t wl t su device pin reset to logic "0" vcc clk internal register q - output active low output register active high output register system power-up, some conditions must be met to provide a valid power-up reset of the ispgal22v10. first, the vcc rise must be monotonic. second, the clock input must be at static ttl level as shown in the diagram during power up. the registers will reset within a maximum of tpr time. as in normal system operation, avoid clock- ing the device until all input and feedback path setup times have been met. the clock must also meet the minimum pulse width requirements. output input (vref typical = 3.2v) vcc pin vref tri-state control active pull-up circuit feedback (to input buffer) pin feedback data output (vref typical = 3.2v) vcc pin vcc vref active pull-up circuit (except sdi on ispgal22v10c) esd protection circuit esd protection circuit vcc pin pull-down resistor (sdi on ispgal22v10c only) input/output equivalent schematics circuitry within the ispgal22v10 provides a reset signal to all reg- isters during power-up. all internal registers will have their q outputs set low after a specified time (tpr, 1 s max). as a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. this feature can greatly simplify state machine design by providing a known state on power-up. the timing diagram for power-up is shown below. because of the asynchronous nature of all devices discontinued
specifications ispgal22v10 12 ispgal22v10c: typical ac and dc characteristic diagrams normalized tpd vs vcc supply voltage (v) normalized tpd 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 normalized tco vs vcc supply voltage (v) normalized tco 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 normalized tsu vs vcc supply voltage (v) normalized tsu 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 normalized tpd vs temp temperature (deg. c) normalized tpd 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 normalized tco vs temp temperature (deg. c) normalized tco 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 normalized tsu vs temp temperature (deg. c) normalized tsu 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -55 -25 0 25 50 75 100 125 delta tpd vs # of outputs switching number of outputs switching delta tpd (ns) -1 -0.75 -0.5 -0.25 0 12345678910 delta tco vs # of outputs switching number of outputs switching delta tco (ns) -1 -0.75 -0.5 -0.25 0 12345678910 delta tco vs output loading output loading (pf) delta tco (ns) -2 0 2 4 6 8 10 12 0 50 100 150 200 250 300 rise fall delta tpd vs output loading output loading (pf) delta tpd(ns) -2 0 2 4 6 8 10 0 50 100 150 200 250 300 rise fall all devices discontinued
specifications ispgal22v10 13 vol vs iol iol (ma) vol (v) 0 0.5 1 1.5 2 2.5 3 0.00 20.00 40.00 60.00 80.00 100.00 voh vs ioh ioh(ma) voh (v) 0 1 2 3 4 5 0.00 10.00 20.00 30.00 40.00 50.00 60.00 voh vs ioh ioh(ma) voh (v) 3.5 3.75 4 4.25 4.5 0.00 1.00 2.00 3.00 4.00 normalized icc vs vcc supply voltage (v) normalized icc 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 normalized icc vs temp temperature (deg. c) normalized icc 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 normalized icc vs freq. frequency (mhz) normalized icc 0.80 0.90 1.00 1.10 1.20 0 25 50 75 100 delta icc vs vcc vin (v) delta icc (ma) 0 1 2 3 4 5 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 input clamp (vik) vik (v) iik (ma) 0 10 20 30 40 50 60 70 80 90 100 -2.00 -1.50 -1.00 -0.50 0.00 ispgal22v10c: typical ac and dc characteristic diagrams all devices discontinued
notes 14 all devices discontinued

▲Up To Search▲

Price & Availability of ISPGAL22V10C-7LK

	To Download ISPGAL22V10C-7LK Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .